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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 1.1 / apr. 2005 1 128mb synchronous dram base d on 2m x 4bank x16 i/o document title 4bank x 2m x 16bits synchronous dram revision history revision no. history draft date remark 1.0 first version release feb. 2005 1.1 changed toh(only symbol ?h?): 2.5ns -> 2.7ns apr. 2005
rev. 1.1 / apr. 2005 2 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series description the hynix hy5v26e(l)f(p)-xxi series is a 134,217,728bit cmos synchronous dram, ideally suited for the memory applications which require wide data i/o and high bandwi dth. hy5v26e(l)f(p)-xxi series is organized as 4banks of 2,097,152 x 16. hy5v26e(l)f(p)-xxi is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data pa ths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), an d the burst count sequence(se- quential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or writ e command on any cycle. (this pipelined design is not re- stricted by a '2n' rule) features ordering information note: 1. hy5v26ef-xxi series: normal power, leaded. 2. hy5v26elf-xxi series: low power, leaded. 3. hy5v26efp-xxi series: normal power, lead free. 4. hy5v26elfp-xxi series: low power, lead free. 5. hy5v26esf(p)-xxi series: super low power; contact hynix office fo r product availability . part no. clock frequency organization interface operation temp. package hy5v26e(l)f(p)-5i 200mhz 4banks x 2mbits x16 lvttl -40 ~ 85 o c 54 ball fbga hy5v26e(l)f(p)-6i 166mhz hy5v26e(l)f(p)-7i 143mhz hy5v26e(l)f(p)-hi 133mhz ? voltage: vdd and vddq 3.3v supply voltage ? all device pins are compatible with lvttl interface ? 54 ball fbga (lead or lead free package) ? all inputs and outputs refere nced to positive edge of system clock ? data mask function by udqm, ldqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency; 2, 3 clocks ? burst read single write operation ? operation temperature : -40 ~ 85 o c
rev. 1.1 / apr. 2005 3 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series ball configuration 54 ball fbga 0.8mm ball pitch 9 8 7 3 21 a b c d e f g h j 54 ball fbga 0.8mm ball pitch 9 8 7 3 21 a b c d e f g h j h j b c d a g f e vss dq14 dq12 dq10 dq8 udqm nc a8 vss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 vssq vddq vssq vddq vss cke a9 a6 a4 vddq vssq vddq vssq vdd /cas ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm /ras ba1 a1 a2 vdd dq1 dq3 dq5 dq7 /we /cs a10 vdd 1 2 3 7 8 9 < top view >
rev. 1.1 / apr. 2005 4 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series functional block diagram 2mbit x 4banks x 16 i/o synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we u/ldqm a0 a1 ba1 ba0 a11 row pre decoder refresh dq0 dq15 x-decoder x-decoder x-decoder x-decoder y-decoder 2mx16 bank 0 2mx16 bank 1 2mx16 bank 2 2mx16 bank 3 memory cell array data out control pipe line control
rev. 1.1 / apr. 2005 5 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series basic functional description mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 op code 00 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0 sequential 1 interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 11 00 1 22 01 0 4 4 01 1 88 10 0 reserved reserved 10 1 reserved reserved 1 10 reserved reserved 1 11 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 reserved
rev. 1.1 / apr. 2005 6 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series absolute maximum rating dc operating condition (t a = -40 o c to 85 o c) note: 1. all voltages are referenced to v ss = 0v 2. v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3. v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration ac operating test condition (t a = -40 o c to 85 o c, v dd =3.3 0.3v, v ss =0v) note: 1. parameter symbol rating unit ambient temperature t a -40 ~ 85 o c o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on vdd relative to vss v dd , v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature / time t solder 260 / 10 o c / sec parameter symbol min. typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1, 2 input low voltage v il -0.3 - 0.8 v 1, 3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4 / 0.4 v input timing measurement reference level voltage v trip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage v outref 1.4 v output load capacitance for access time measurement cl 50 pf 1 z0 = 50 output output vtt = 1.4v 50pf rt = 50 vtt = 1.4v 50pf dc output load circuit ac output load circuit rt = 500 ? ? ?
rev. 1.1 / apr. 2005 7 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series capacitance (t a = -40 o c to 85 o c, f=1mhz, v dd =3.3v) dc characteristics i (t a = -40 o c to 85 o c) note: 1. v in = 0 to 3.3v, all other balls are not tested under v in =0v 2. d out is disabled, v out =0 to 3.6 parameter pin symbol min max unit input capacitance clk ci1 2.0 4.0 pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , ldqm, udqm ci2 2.0 4.0 pf data input / output capacitance dq0 ~ dq15 ci/o 3.0 5.5 pf parameter symbol min max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma
rev. 1.1 / apr. 2005 8 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series dc characteristics ii (t a = -40 o c to 85 o c) note: 1. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3. hy5v26ef(p) series: normal power hy5v26elf(p) series: low power hy5v26esf(p)-xxi series: super low power; contact hynix office fo r product availability . parameter symbol test condition speed unit note 5 6 7 h operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 120 110 100 100 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 2 ma i dd2ps cke v il (max), t ck = 2ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 18 ma i dd2ns cke v ih (min), t ck = input signals are stable. 15 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 5 ma i dd3ps cke v il (max), t ck = 5 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 40 ma i dd3ns cke v ih (min), t ck = input signals are stable. 35 burst mode operating cur- rent i dd4 t ck t ck (min), i ol =0ma all banks active 120 110 100 100 ma 1 auto refresh current i dd5 t rc t rc (min), all banks active 210 200 190 190 ma 2 self refresh current i dd6 cke 0.2v normal 2 ma 3 low power 800 ua
rev. 1.1 / apr. 2005 9 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series ac characteristics i (ac operating conditions unless otherwise noted) note: 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with in put signals of 1v/ns edge rate, from 0.8v to 0.2v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter sym- bol 5 6 7 h unit note min max min max min max min max system clock cycle time cl = 3 t ck3 5.0 1000 6.0 1000 7.0 1000 7.5 1000 ns cl = 2 t ck2 10 10 10 10 ns clock high pulse width t chw 1.75-2.0-2.0-2.5- ns 1 clock low pulse width t clw 1.75-2.0-2.0-2.5- ns 1 access time from clock cl = 3 t ac3 -4.5-5.4-5.4-5.4 ns 2 cl = 2 t ac2 -6.0-6.0-6.0-6.0 ns data-out hold time t oh 2.0 - 2.0 - 2.5 - 2.7 - ns data-input setup time t ds 1.5 - 1.5 - 1.5 - 1.5 - ns 1 data-input hold time t dh 0.8 - 0.8 - 0.8 - 0.8 - ns 1 address setup time t as 1.5 - 1.5 - 1.5 - 1.5 - ns 1 address hold time t ah 0.8 - 0.8 - 0.8 - 0.8 - ns 1 cke setup time t cks 1.5 - 1.5 - 1.5 - 1.5 - ns 1 cke hold time t ckh 0.8 - 0.8 - 0.8 - 0.8 - ns 1 command setup time t cs 1.5 - 1.5 - 1.5 - 1.5 - ns 1 command hold time t ch 0.8 - 0.8 - 0.8 - 0.8 - ns 1 clk to data output in low-z time t olz 1.0 - 1.0 - 1.5 - 1.5 - ns clk to data output in high-z time cl = 3 t ohz3 -4.5-5.4-5.4-5.4ns cl = 2 t ohz2 -6.0-6.0-6.0-6.0ns
rev. 1.1 / apr. 2005 10 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series ac characteristics ii (ac operating conditions unless otherwise noted) note: 1. a new command can be given t rrc after self refresh exit. parameter symbol 5 6 7 h uni t not e min max min max min max min max ras cycle time operation t rc 55 - 60 - 63 - 63 - ns ras cycle time auto refresh t rrc 55 - 60 - 63 - 63 - ns ras to cas delay t rcd 15 - 18 - 20 - 20 - ns ras active time t ras 38.7 100k 42 100k 42 100k 42 120 k ns ras precharge time t rp 15 - 18 - 20 - 20 - ns ras to ras bank active delay t rrd 10 - 12 - 14 - 15 - ns cas to cas delay t ccd 1-1-1-1-clk write command to data-in delay t wtl 0 -0 -0 -0 -clk data-in to precharge command t dpl 2-2-2-2-clk data-in to active command t dal t dpl + t rp dqm to data-out hi-z t dqz 2-2-2-2-clk dqm to data-in mask t dqm 0-0-0-0-clk mrs to new command t mrd 2-2-2-2-clk precharge to data output high-z cl = 3 t proz3 3-3-3-3-clk cl = 2 t proz2 2-2-2-2-clk power down exit time t dpe 1-1-1-1-clk self refresh exit time t sre 1-1-1-1-clk1 refresh time t ref -64-64-64-64ms
rev. 1.1 / apr. 2005 11 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series command truth table command cken-1 cken cs ras cas we dqm addr a10/ap ba note mode register set h x l l l l x op code no operation h x hx xx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l l x a9 ball high (other balls op code) mrs mode self refresh 1 entry h l l l l h x x exit l h hx xx x lhhh precharge power down entry h l hx xx x x lhhh exit l h hx xx x lhhh clock suspend entry h l hx xx x x lvvv exit l h x x
rev. 1.1 / apr. 2005 12 synchronous dram memory 128mbit (8mx16bit) hy5v26e(l)f(p)-xxi series package information 54 ball fbga 8.0mm x 8.0mm unit [mm] 1.20 max 0.340 0.05 0.450 0.05 8.0 6.40 bsc 0.80(typ) a1 index mark 8.00 0.80(typ) 6.40 4.00 0.05 bottom view 0.8 3.20 0.05

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